High power RF & microwave transistor devices are typically connected to package leads and other electronic components using multiple parallel wires, or “wirebond arrays.” While single wires are often modeled as inductors in series with resistors, wirebond arrays are typically modeled as a number of inductors connected in parallel, wherein mutual coupling between wires is factored in to produce a single equivalent inductance.
The input impedance (Zin) of high power transistors is typically low (less than approximately 3.0 Ω). At high frequencies (e.g., greater than about 2.0 GHz), it is desirable that the interconnecting input wirebond array be low inductance to enable broadband impedance matching. Reducing impedance is also important, to a lesser extent, at lower frequencies (e.g., broadcast frequencies of about 450 MHz.) If the inductance of the input wirebond array is too large, the quality (Q) of the matching network becomes excessive and broadband impedance matching can no longer be achieved.
The inductance of a wirebond array is a function of wire length, number of wires, wire loop height, and distance between the wires and the ground plane. In most applications, the physical dimensions of the design are predefined (e.g., component size, package size, etc.) and minimum loop height wires are typically already used. Thus, efforts to reduce wirebond array impedance have centered primarily on increasing the number of wires. Increasing the number of wires also increases the size of the device and/or package and requires additional processing steps.
Furthermore, in traditional wirebond arrays, the RF current is increased on the outer wires of the array. The resulting uneven current distribution can lead to an asymmetrical match of the power transistor. Furthermore, this non-symmetrical current can cause non-symmetrical wire temperatures. Wires at the periphery of the array will become hotter than wires toward the middle, and elevated wire temperatures and high-current operation decreases wire lifetime. This problem is expected to be more severe in the future, as devices with greater power densities (e.g., SiC and GaN devices) are developed.
Accordingly, there is a need for wire-bonding schemes that reduce overall inductance and improve current distribution in wirebond arrays. Other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.